PM0214 datasheet(150/245 Pages) STMICROELECTRONICS

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The STM32 Cortex-M4 instruction set

PM0214

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DocID022708 Rev 4

3.10.2

VADD

Floating-point Add

Syntax

VADD{cond}.F32 {Sd,} Sn, Sm

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

‘Sd’ is the destination floating-point value

•

‘Sn, Sm’ are the operand floating-point values.

Operation

This instruction:

Adds the values in the two floating-point operand registers.

Places the results in the destination floating-point register.

Restrictions

There are no restrictions.

Condition flags

This instruction does not change the flags.

Examples

VADD.F32 S4, S6, S7

3.10.3

VCMP, VCMPE

Compares two floating-point registers, or one floating-point register and zero.

Syntax

VCMP{E}{cond}.F32 Sd, Sm

VCMP{E}{cond}.F32 Sd, #0.0

where:

•

‘cond’ is an optional condition code, see Conditional execution on page 64.

•

‘E’ If present, any NaN operand causes an Invalid Operation exception. Otherwise,

only a signaling NaN causes the exception.

•

‘Sd’ is the floating-point operand to compare.

•

‘Sm’ is the floating-point operand that is compared with

Operation

This instruction:

Compares:

Two floating-point registers.

One floating-point register and zero.

Writes the result to the FPSCR flags.

Restrictions

This instruction can raise an Invalid Operation exception if either operand is any type of

NaN. It always raises an Invalid

Operation exception if either operand is a signaling NaN.

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