PM0214 datasheet(193/245 Pages) STMICROELECTRONICS

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PM0214

Core peripherals

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4.3

Nested vectored interrupt controller (NVIC)

This section describes the Nested Vectored Interrupt Controller (NVIC) and the registers it

uses. The NVIC supports:

•

Up to 81 interrupts (interrupt number depends on the STM32 device type; refer to the

datasheets)

•

A programmable priority level of 0-15 for each interrupt. A higher level corresponds to a

lower priority, so level 0 is the highest interrupt priority

•

Level and pulse detection of interrupt signals

•

Dynamic reprioritization of interrupts

•

Grouping of priority values into group priority and subpriority fields

•

Interrupt tail-chaining

•

An external Non-maskable interrupt (NMI)

The processor automatically stacks its state on exception entry and unstacks this state on

exception exit, with no instruction overhead. This provides low latency exception handling.

The hardware implementation of the NVIC registers is:

Table 45. NVIC register summary

Address

Name

Type

Required

privilege

Reset value

Description

0xE000E100-

0xE000E10B

NVIC_ISER0-

NVIC_ISER2

Privileged

0x00000000

Table 4.3.2: Interrupt set-enable registers

(NVIC_ISERx) on page 195

0XE000E180-

0xE000E18B

NVIC_ICER0-

NVIC_ICER2

Privileged

0x00000000

Table 4.3.3: Interrupt clear-enable registers

(NVIC_ICERx) on page 196

0XE000E200-

0xE000E20B

NVIC_ISPR0-

NVIC_ISPR2

Privileged

0x00000000

Table 4.3.4: Interrupt set-pending registers

(NVIC_ISPRx) on page 197

0XE000E280-

0xE000E29C

NVIC_ICPR0-

NVIC_ICPR2

Privileged

0x00000000

Table 4.3.5: Interrupt clear-pending registers

(NVIC_ICPRx) on page 198

0xE000E300-

0xE000E31C

NVIC_IABR0-

NVIC_IABR2

Privileged

0x00000000

Table 4.3.6: Interrupt active bit registers

(NVIC_IABRx) on page 199

0xE000E400-

0xE000E503

NVIC_IPR0-

NVIC_IPR20

Privileged

0x00000000

Table 4.3.7: Interrupt priority registers

(NVIC_IPRx) on page 200

0xE000EF00

STIR

Configurable 0x00000000

Table 4.3.8: Software trigger interrupt register

(NVIC_STIR) on page 201

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