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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PM0214 데이터시트(PDF) 195 Page - STMicroelectronics |
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PM0214 데이터시트(HTML) 195 Page - STMicroelectronics |
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195 / 245 page  DocID022708 Rev 4 195/245 PM0214 Core peripherals 244 4.3.2 Interrupt set-enable registers (NVIC_ISERx) Address offset: 0x00 - 0x0B Reset value: 0x0000 0000 Required privilege: Privileged 31 3029 28 27 26 25 24 23 22 21 20 19 18 17 16 SETENA[31:16] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs 15 14 13 12 11 10 9 8 76 54 3 21 0 SETENA[15:0] rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs rs Bits 31:0 SETENA: Interrupt set-enable bits. Write: 0: No effect 1: Enable interrupt Read: 0: Interrupt disabled 1: Interrupt enabled. If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority. |
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