PM0215 datasheet(17/91 Pages) STMICROELECTRONICS

17 / 91 page

PM0215

The STM32 Cortex-M0 processor

Doc ID 022979 Rev 1

17/91

2.1.4

Exceptions and interrupts

The Cortex-M0 processor supports interrupts and system exceptions. The processor and

the NVIC prioritize and handle all exceptions. An exception changes the normal flow of

software control. The processor uses handler mode to handle all exceptions except for

reset. See Exception entry on page 26 and Exception return on page 27 for more

information. The NVIC registers control interrupt handling. See Nested vectored interrupt

controller (NVIC) on page 70 for more information.

2.1.5

Data types

The processor manages all memory accesses as little-endian. See Memory regions, types

and attributes on page 19 for more information. It supports the following data types:

●

32-bit words

●

16-bit halfwords

●

8-bit bytes

2.1.6

The Cortex microcontroller software interface standard (CMSIS)

ARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) for

programming Cortex-M0 microcontrollers. The CMSIS is an integrated part of the device

driver library. For a Cortex-M0 microcontroller system, the Cortex Microcontroller Software

Interface Standard (CMSIS) defines:

●

A common way to:

–

Access peripheral registers

–

Define exception vectors

●

The names of:

–

The registers of the core peripherals

–

The core exception vectors

●

A device-independent interface for RTOS kernels.

The CMSIS includes address definitions and data structures for the core peripherals in the

Cortex-M0 processor.

The CMSIS simplifies software development by enabling the reuse of template code and the

combination of CMSIS-compliant software components from various middleware vendors.

Software vendors can expand the CMSIS to include their peripheral definitions and access

functions for those peripherals.

This document includes the register names defined by the CMSIS, and gives short

descriptions of the CMSIS functions that address the processor core and the core

peripherals.

Note:

This document uses the register short names defined by the CMSIS. In a few cases these

differ from the architectural short names that might be used in other documents.

The following sections give more information about the CMSIS:

●

Power management programming hints on page 30

●

CMSIS intrinsic functions on page 35

●

Interrupt set-enable register (ISER) on page 71

●

NVIC programming hints on page 75

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