UM0843 datasheet(11/48 Pages) STMICROELECTRONICS

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UM0843

Block descriptions

Doc ID16543 Rev 2

11/48

Block descriptions

6.1

MII Ethernet

There is one MII Ethernet PHY available on the board at U24, connected through the media

independent interface to the Ethernet MAC on the CPU processor.

By default the MII address of the MII Ethernet PHY is selected as shown in Table 1.

By default the initial configuration of the MII Ethernet PHY is selected as shown in Table 2.

There are two LEDs embedded in each RJ45 connector (U25) which are used to indicate

the status of the line:

●

The green LED in the connector is driven on continuously when the Ethernet link is

established with the counterpart.

●

The yellow LED in the connector blinks when there is TX or RX activity.

The Serial Management Interface (SMI) is part of the MII interface and is used to transfer

management information between MAC and PHY (access to the PHY registers).

For the correct functionality of the MII Ethernet PHY (U24 in MII mode), it is necessary to

clock with a by 25 MHz clock. The default option is to use oscillator OSC1.

6.2

SMII Ethernet

There are four SMII Ethernet PHYs available on the board at U18, U19, U20 and U21,

connected through serial media independent interfaces to the Ethernet MACs in the

SPEAr310 MPU.

By default the SMII addresses of the SMII Ethernet PHYs are selected as shown in Table 3.

Table 1.

MII address of the MII Ethernet PHY at U24

Component

MII address

U24

0x04

Table 2.

Default configuration of the Ethernet PHY in U24

Function

Default configuration

Auto negotiation

Enabled

10/100 Mbits

100 Mbits selected for auto negotiation

Half/Full duplex

Full duplex selected for auto negotiation

Internal loopback

Disabled

Power down

Disabled (PHY active)

MII/RMII mode

MII selected

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