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UM0851

Non-volatile memory device drivers

Doc ID 16604 Rev 2

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Non-volatile memory device drivers

Non-volatile memory can retain stored information even when not powered, and it is a

fundamental feature of an embedded system.

The following section groups the drivers related to the non-volatile memory controllers

embedded in SPEAr.

5.1

NAND Flash driver

5.1.1

Hardware overview

NAND Flash is a non-volatile memory with a data access width of 8 or 16 bits. The read and

write operations are done in pages (typically 512 or 2048 bytes) while the erase operation is

done in erase blocks (block size is typically 16 K or 64 K). NAND Flash is I/O mapped and

requires a relatively complicated driver for any operation.

Nowadays the NAND technology allows bigger size parts at lower cost, but with a lower

reliability. The main issues the NAND technology has to face are bit-flipping and bad-blocks.

To correct bit-flipping, NAND controller and driver uses error detection /correction code

(EDC/ECC). The second issue requires the use of some bad-block management

techniques.

Higher density, lower cost, faster write/erase times, and a longer re-write life expectancy

make NAND Flash especially well suited for consumer media applications such as USB

Flash drives, digital cameras and MP3 players in which large files of sequential data need to

be loaded into memory quickly and replaced with new files repeatedly.

The FSMC (flexible static memory controller) controls the NAND Flash in the SPEAr

platform. The main features of the FSMC are:

●

It provides programmable timings to support a wide range of devices. It supports

programmable wait states, bus turn around cycles as well as output enable and write

enable delays.

●

It provides an interface between the AHB system bus and Nand Flash memory devices.

●

It can do the ECC calculation for the NAND Flash.

●

When using the FSMC wait feature, the controller waits for the NAND Flash to indicate

that it is ready. For this, the ready/busy pin of the NAND Flash should be connected to

the FSMC wait pin and then the wait bit should be enabled in the control register.

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