 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
UPD72042 데이터시트(PDF) 2 Page - NEC |
|
|
|||||||||||||||||||||||||||||
UPD72042 데이터시트(HTML) 2 Page - NEC |
|
|
2 / 92 page  µPD72042 2 Data Sheet S14870EJ1V0DS00 PIN CONFIGURATION (TOP VIEW) • 16-pin plastic SOP (9.53 mm (375)) µPD72042GT Note Parentheses indicate the state corresponding to two-wire serial I/O mode. AVDD : Main power supply for IEBus (connected to the VDD pin) BUS–, BUS+ : IEBus I/O C/D : Command/data switch input CS : Chip select input GND : Ground IRQ : Interrupt request output NC : No connection RESET : Reset input SCK : Serial clock input SEL : Serial mode selection SI : Serial data input SIO : Serial data I/O SO : Serial data output TEST : Test input (connected to the VDD pin) VDD : Main power supply XI, XO : System clock 1 2 3 4 5 6 7 8 VDD TEST RESET CS SEL AVDD BUS + BUS − 16 15 14 13 12 11 10 9 SCK SI(SIO) Note SO(NC) Note IRQ C/D XI XO GND |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
