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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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UPD72042 데이터시트(PDF) 21 Page - NEC |
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UPD72042 데이터시트(HTML) 21 Page - NEC |
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21 / 92 page  µPD72042 21 Data Sheet S14870EJ1V0DS00 2.5 BIT FORMAT Fig. 2-4 illustrates the bits that constitute an IEBus communication frame. Fig. 2-4 IEBus Bit Format (Concept) Preparation period : First and subsequent low-level (logic 1) periods Synchronization period : Next high-level (logic 0) period Data period : Period in which a bit value is indicated (logic 1 = low level, logic 0 = high level) The synchronization and data periods are almost equal in duration. For the IEBus, synchronization is established for each bit. The specifications of the total time required for a bit and the duration of each period allotted within the bit vary depending on the type of the transmission bits, and whether the unit is a master or slave. Logic "1" Logic "0" Preparation period Synchronization period Data period Preparation period Synchronization period Data period Logic 1: The potential difference between the bus lines (the BUS+ and BUS- pins) is 20 mV or less (low level). Logic 0: The potential difference between the bus lines (the BUS+ and BUS- pins) is 120 mV or more (high level). |
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