PM0223 datasheet(10/110 Pages) STMICROELECTRONICS

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PM0223

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DocID025763 Rev 1

The STM32L0 Cortex-M0+ processor closely integrates a configurable Nested Vectored

Interrupt Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:

•

Includes a Non-Maskable Interrupt (NMI).

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Provides zero jitter interrupt option.

•

Provides four interrupt priority levels.

The tight integration of the processor core and NVIC provides fast execution of Interrupt

Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved through

the hardware stacking of registers, and the ability to abandon and restart load-multiple and

store-multiple operations. Interrupt handlers do not require any assembler wrapper code,

removing any code overhead from the ISRs. Tail-chaining optimization also significantly

reduces the overhead when switching from one ISR to another.

To optimize low-power designs, the NVIC integrates with the sleep modes, that include a

deep sleep function that enables the entire device to be rapidly powered down.

1.3.1

System-level interface

The STM32L0 Cortex-M0+ processor provides a single system-level interface using AMBA

technology to provide high speed, low latency memory accesses.

The STM32L0 Cortex-M0+ processor has an optional Memory Protection Unit (MPU) that

provides fine grain memory control, enabling applications to use multiple privilege levels,

separating and protecting code, data and stack on a task-by-task basis. Such requirements

are becoming critical in many embedded applications such as automotive systems.

1.3.2

Integrated configurable debug

The STM32L0 Cortex-M0+ processor implements a complete hardware debug solution, with

extensive hardware breakpoint and watchpoint options. This provides high system visibility

of the processor, memory and peripherals through a <2-pin Serial Wire Debug (SWD) port>

that is ideal for microcontrollers and other small package devices.

1.3.3

STM32L0 Cortex-M0+ processor features summary

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Thumb instruction set with Thumb-2 Technology.

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High code density with 32-bit performance.

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User and Privileged mode execution.

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Tools and binary upwards compatible with Cortex-M processor family.

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Integrated ultra low-power sleep modes.

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Efficient code execution enabling slower processor clock or increased sleep time.

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Single-cycle 32-bit hardware multiplier.

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Zero jitter interrupt handling.

•

Memory Protection Unit (MPU) for safety-critical applications.

•

Low latency, high-speed peripheral I/O port.

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A Vector Table Offset Register.

•

Extensive debug capabilities.

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