PM0223 datasheet(22/110 Pages) STMICROELECTRONICS

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The STM32L0 Cortex-M0+ Processor

PM0223

22/110

DocID025763 Rev 1

Table 10. Ordering of memory accesses(1)

1. - Means that the memory system does not guarantee the ordering of the accesses

< Means that accesses are observed in program order, that is A1 is always observed before A2.

2.2.3

Behavior of memory accesses

The behavior of accesses to each region in the memory map is:

The Code, SRAM, and external RAM regions can hold programs.

The MPU can override the default memory access behavior described in this section. For

more information, see 4.5: Memory Protection Unit on page 98.

Table 11. Memory access behavior(1)

1. See Memory regions, types and attributes on page 20 for more information.

Address range

Memory region

Memory type

Description

0x00000000-

0x1FFFFFFF

Code

Normal

Executable region for

program code. You can

also put data here.

0x20000000-

0x3FFFFFFF

SRAM

Normal

Executable region for

data. You can also put

code here.

0x40000000-

0x5FFFFFFF

Peripheral

Device

External device memory.

0x60000000-

0x9FFFFFFF

External RAM

Normal

Executable region for

data.

0xA0000000-

0xDFFFFFFF

External device

Device

External device memory.

0xE0000000-

0xE00FFFFF

Private Peripheral

Bus

Strongly- ordered

This region includes the

NVIC, System timer, and

System Control Block.

Only word accesses can

be used in this region.

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