Peripherals interconnect matrix

AN4640

12/19

DocID027335 Rev 2

This feature is described in the following sections of the RM0090 and RM0390 reference

manuals:

•

“Internal/external clock measurement using TIM5/TIM11”;

•

“TIM5 option register (TIM5_OR)”;

•

“TIM11 option register 1 (TIM11_OR)”.

2.4

System block

Power supplies block includes:

•

The internal reference voltage VREFINT;

•

VBAT;

•

External interrupt/event controller (EXTI).

2.4.1

From VBAT, VREFIN to ADC

The VBAT channel is connected to channel ADC1_IN18. It can be converted as an injected

or regular channel.

The VREFINT is connected to ADC1_IN17.

Refer to the following sections of the RM0090 and RM0390 reference manuals for a

description of the interconnection between VBAT, VREFINT and ADC:

•

“Channel selection”;

•

“Battery charge monitoring”.

2.4.2

From EXTI to Analog block

EXTI can be used to generate an ADC triggering event or to start a DAC conversion.

ADC synchronization is described in the “Conversion on external trigger and trigger polarity”

section of the RM0390 and RM0090 reference manuals, while selection of input triggers on

DAC is provided in the “DAC trigger selection” section of the same documents.

2.5

Communication interfaces block

2.5.1

From SPIDIFRX to TIM

SPIDIFRX (SPDIFRX_FRAME_SYNC) is connected to TIM11_CH1 to measure the clock

drift of received SPDIFRX frames.

This interconnection is explained in the section “TIM11 option register 1 (TIM11_OR)” of the

RM0390 reference manual.

2.5.2

From USB block to TIM

USB block includes:

•

USB on-the-go full-speed (OTG_FS);

•

USB on-the-go high-speed (OTG_HS).