LT1767 datasheet(13/16 Pages) LINER

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LT1767/LT1767-1.8/

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sn1767 1767fas

APPLICATIONS INFORMATION

Notice that the catch diode’s forward voltage contributes

a significant loss in the overall system efficiency. A larger,

lower VF diode can improve efficiency by several percent.

PINDUCTOR = (ILOAD) (LDCR)

LDCR = Inductor DC resistance (assume 0.1Ω)

PINDUCTOR = (1) (0.1) = 0.1W

Typical thermal resistance of the board is 35

°C/W. At an

ambient temperature of 65

°C,

Tj = 65 + 40 (0.4) + 35 (0.39) = 95°C

If a true die temperature is required, a measurement of the

SYNC to GND pin resistance can be used. The SYNC pin

resistance across temperature must first be calibrated,

with no device power, in an oven. The same measurement

can then be used in operation to indicate the die tempera-

ture.

FREQUENCY COMPENSATION

Before starting on the theoretical analysis of frequency

response, the following should be remembered – the

worse the board layout, the more difficult the circuit will be

to stabilize. This is true of almost all high frequency analog

circuits, read the ‘LAYOUT CONSIDERATIONS’ section

first. Common layout errors that appear as stability prob-

lems are distant placement of input decoupling capacitor

and/or catch diode, and connecting the VC compensation

to a ground track carrying significant switch current. In

addition, the theoretical analysis considers only first order

non-ideal component behavior. For these reasons, it is

important that a final stability check is made with produc-

tion layout and components.

The LT1767 uses current mode control. This alleviates

many of the phase shift problems associated with the

inductor. The basic regulator loop is shown in Figure 7,

with both tantalum and ceramic capacitor equivalent cir-

cuits. The LT1767 can be considered as two gm blocks, the

error amplifier and the power stage.

Figure 8 shows the overall loop response with a 330pF VC

capacitor and a typical 100

µF tantalum output capacitor.

The response is set by the following terms:

Error amplifier:

DC gain set by gm and RL = 850µ • 500k = 425.

Pole set by CF and RL = (2π • 500k • 330p)–1 = 965Hz.

Unity-gain set by CF and gm = (2π • 330p • 850µ–1)–1 =

410kHz.

Power stage:

DC gain set by gm and RL (assume 10Ω) = 2.5 • 10 = 25.

Pole set by COUT and RL = (2π • 100µ • 10)–1 = 159Hz.

Unity-gain set by COUT and gm = (2π • 100µ • 2.5–1)–1 =

3.98kHz.

Tantalum output capacitor:

Zero set by COUT and CESR = (2π • 100µ• 0.1)–1 = 15.9kHz.

Figure 8. Overall Loop Response

Figure 7. Model for Loop Response

1.2V

VSW

LT1767

GND

1767 F07

OUTPUT

ESR

500k

ERROR

AMPLIFIER

CURRENT MODE

POWER STAGE

gm = 2.5mho

gm =

850

µmho

ESL

CERAMIC

TANTALUM

FREQUENCY (Hz)

–20

–40

180

150

120

1767 F10

GAIN

PHASE

VOUT = 5V

COUT = 100µF, 0.1Ω

CC = 330pF

RC/CF = N/C

ILOAD = 500mA

10k

100

100k

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