14

LT1767/LT1767-1.8/

LT1767-2.5/LT1767-3.3/LT1767-5

sn1767 1767fas

The zero produced by the ESR of the tantalum output

capacitor is very useful in maintaining stability. Ceramic

output capacitors do not have a zero due to very low ESR,

but are dominated by their ESL. They form a notch in the

be made dominant. A typical value of 2.2nF will achieve

this.

If better transient response is required, a zero can be

transient response will generally improve, but two effects

limit its value. First, the combination of output capacitor

gether. Second, if the loop gain is not rolled sufficiently at

pin enough to cause unstable duty cycle switching similar

to subharmonic oscillation. This may not be apparent at

the output. Small signal analysis will not show this since

a continuous time system is assumed. If needed, an

When checking loop stability, the circuit should be oper-

ated over the application’s full voltage, current and tem-

perature range. Any transient loads should be applied and

the output voltage monitored for a well-damped behavior.

See Application Note 76 for more details.

CONVERTER WITH BACKUP OUTPUT REGULATOR

In systems with a primary and backup supply, for ex-

ample, a battery powered device with a wall adapter input,

the output of the LT1767 can be held up by the backup

supply with its input disconnected. In this condition, the

is held at ground, only the shut down current of 6

µA will

be pulled via the SW pin from the second supply. With the

SHDN pin floating, the LT1767 will consume its quiescent

current to any other components connected to the input

line. If this load is greater than 10mA or the input could be

shorted to ground, a series Schottky diode must be added,

as shown in Figure 9. With these safeguards, the output

rating.

BUCK CONVERTER WITH ADJUSTABLE SOFT-START

Large capacitive loads or high input voltages can cause

high input currents at start-up. Figure 10 shows a circuit

that limits the dv/dt of the output at start-up, controlling

the capacitor charge rate. The buck converter is a typical

the output starts to rise, Q1 turns on, regulating switch

output. Output rise time is controlled by the current

is in regulation, Q1 turns off and the circuit operates

normally. R3 is transient protection for the base of Q1.

RiseTime

RC

V

V

SS

OUT

BE

=

()(

)(

)

()

4

Using the values shown in Figure 10,

RiseTime

ms

==

(•

)(

•

)( )

.

–

47 10

15 10

5

07

5

39

The ramp is linear and rise times in the order of 100ms are

possible. Since the circuit is voltage controlled, the ramp

rate is unaffected by load characteristics and maximum

output current is unchanged. Variants of this circuit can be

used for sequencing multiple regulator outputs.

Dual Output SEPIC Converter

The circuit in Figure 11 generates both positive and

negative 5V outputs with a single piece of magnetics. The

two inductors shown are actually just two windings on a

standard B H Electronics inductor. The topology for the 5V

output is a standard buck converter. The – 5V topology

would be a simple flyback winding coupled to the buck

converter if C4 were not present. C4 creates a SEPIC

(single-ended primary inductance converter) topology

which improves regulation and reduces ripple current in

L1. Without C4, the voltage swing on L1B compared to

L1A would vary due to relative loading and coupling

losses. C4 provides a low impedance path to maintain an

equal voltage swing in L1B, improving regulation. In a

flyback converter, during switch on time, all the converter’s

energy is stored in L1A only, since no current flows in L1B.

At switch off, energy is transferred by magnetic coupling

into L1B, powering the – 5V rail. C4 pulls L1B positive