8

LTC1279

TEST CIRCUITS

Load Circuits for Output Float Delay

Load Circuits for Access Timing

3k

DBN

DGND

DBN

3k

5V

DGND

1279 TC01

3k

10pF

DBN

DGND

10pF

DBN

3k

5V

DGND

1279 TC02

CS to RD Setup Timing

SHDN to CONVST Wake-Up Timing

CS to CONVST Setup Timing

TI I G DIAGRA S

CONVERSION DETAILS

The LTC1279 uses a successive approximation algorithm

and an internal sample-and-hold circuit to convert an

analog signal to a 12-bit parallel output. The ADC is

complete with a precision reference and an internal clock.

The control logic provides easy interface to microproces-

sors and DSPs. (Please refer to the Digital Interface

section for the data format.)

Conversion start is controlled by the CS and CONVST

inputs. At the start of conversion the successive approxi-

mation register (SAR) is reset. Once a conversion cycle

has begun it cannot be restarted.

During conversion, the internal 12-bit capacitive DAC

output is sequenced by the SAR from the most significant

bit (MSB) to the least significant bit (LSB). Referring to

capacitor during the acquire phase, and the comparator

offset is nulled by the feedback switch. In this acquire

phase, a minimum delay of 160ns will provide enough

1279 F01

+

–

DAC

SAMPLE

HOLD

S

A

R

12-BIT

LATCH

COMPAR-

ATOR

SAMPLE

SI

SHDN

CONVST

1279 TD03

CS

RD

1279 TD01

CS

CONVST

1279 TD02

time for the sample-and-hold capacitor to acquire the

analog signal. During the convert phase, the comparator

feedback switch opens, putting the comparator into the

ground, injecting the analog input charge onto the sum-

ming junction. This input charge is successively com-