7

LTC1279

PI FU CTIO S

(Bipolar).

(10

µF tantalum in parallel with 0.1µF ceramic).

AGND (Pin 3): Analog Ground.

D11 to D4 (Pins 11 to 4): Three-State Data Outputs.

D11 is the Most Significant Bit.

DGND (Pin 12): Digital Ground.

D3 to D0 (Pins 13 to 16): Three-State Data Outputs.

SHDN (Pin 18): Power Shutdown. The LTC1279 pow-

ers down when SHDN is low.

CONVST (Pin 19): Conversion Start Input. It is active

low. The falling edge of the CONVST signal initiates a

conversion. The LTC1279 responds to CONVST signal

only if the signal applied to CS is a logic low.

RD (Pin 20): READ Input. A logic low signal applied to

this pin enables the output data drivers when the signal

applied to the CS pin is a logic low.

CS (Pin 21): The CHIP SELECT input must be a logic low

for the ADC to recognize the signals applied to the

CONVST and RD inputs.

BUSY (Pin 22): The BUSY output shows the converter

status. It is a logic low during a conversion.

operation. Bypass to AGND with 0.1

µF ceramic. Tie to

analog ground to select unipolar operation.

(10

µF tantalum in parallel with 0.1µF ceramic).

FU CTIO AL BLOCK DIAGRA

12-BIT CAPACITIVE DAC

COMPAR-

ATOR

2.42V REF

SUCCESSIVE APPROXIMATION

REGISTER

OUTPUT LATCHES

•

•

•

D11

D0

BUSY

CONTROL LOGIC

CS

CONVST

RD

SHDN

INTERNAL

CLOCK

ZEROING

SWITCH

(0V FOR UNIPOLAR MODE

OR –5V FOR BIPOLAR MODE)

AGND

DGND

12

12

1279 BD