전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

LTC1409CSW 데이터시트(PDF) 6 Page - Linear Technology

부품명 LTC1409CSW
상세설명  12-Bit, 800ksps Sampling A/D Converter with Shutdown
PDF  20 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  LINER [Linear Technology]
홈페이지  http://www.linear.com
Logo LINER - Linear Technology

LTC1409CSW 데이터시트(HTML) 6 Page - Linear Technology

Back Button LTC1409CSW Datasheet HTML 2Page - Linear Technology LTC1409CSW Datasheet HTML 3Page - Linear Technology LTC1409CSW Datasheet HTML 4Page - Linear Technology LTC1409CSW Datasheet HTML 5Page - Linear Technology LTC1409CSW Datasheet HTML 6Page - Linear Technology LTC1409CSW Datasheet HTML 7Page - Linear Technology LTC1409CSW Datasheet HTML 8Page - Linear Technology LTC1409CSW Datasheet HTML 9Page - Linear Technology LTC1409CSW Datasheet HTML 10Page - Linear Technology Next Button
Zoom Inzoom in Zoom Outzoom out
 6 / 20 page
background image
6
LTC1409
TYPICAL PERFORMANCE CHARACTERISTICS
Input Common Mode Rejection vs
Input Frequency
Power Supply Feedthrough vs
Ripple Frequency
RIPPLE FREQUENCY (Hz)
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
1k
100k
1M
10M
LTC1409 • TPC08
10k
VSS
VDD
DGND
INPUT FREQUENCY (Hz)
1k
80
70
60
50
40
30
20
10
0
10k
100k
LT1409 • TPC09
1M
10M
D3 to D0 (Pins 15 to 18): Three-State Data Outputs.
OGND (Pin 19): Digital Ground for Output Drivers. Tie
to AGND.
NAP/SLP (Pin 20): Power Shutdown Mode. Selects the
mode invoked by the SHDN pin. Low selects Sleep
mode and high selects quick wake-up Nap mode.
SHDN (Pin 21): Power Shutdown Input. A low logic
level will invoke the Shutdown mode selected by the
NAP/SLP pin.
RD (Pin 22): Read Input. This enables the output
drivers when CS is low.
PI FU CTIO S
+AIN (Pin 1): Positive Analog Input, ±2.5V.
–AIN (Pin 2): Negative Analog Input, ±2.5V.
VREF (Pin 3): 2.50V Reference Output.
REFCOMP (Pin 4): 4.06V Reference Output. Bypass to
AGND using 10
µF tantalum in parallel with 0.1µF or
10
µF ceramic.
AGND (Pin 5): Analog Ground.
D11 to D4 (Pins 6 to 13): Three-State Data Outputs.
DGND (Pin 14): Digital Ground for Internal Logic. Tie to
AGND.
Integral Nonlinearity vs
Output Code
OUTPUT CODE
0
1.00
0.50
0
–0.50
–1.00
512 1024 1536 2048
LT1409 • TPC07
2560 3072 3584 4096
Differential Nonlinearity vs
Output Code
OUTPUT CODE
0
1.00
0.50
0
–0.50
–1.00
512 1024 1536 2048
LT1409 • TPC06
2560 3072 3584 4096



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com