LTC1409CSW datasheet(7/20 Pages) LINER

7 / 20 page

LTC1409

PI FU CTIO S

CONVST (Pin 23): Conversion Start Signal. This active

low signal starts a conversion on its falling edge.

CS (Pin 24): Chip Select. The input must be low for the

ADC to recognize CONVST and RD inputs.

BUSY (Pin 25): The BUSY output shows the converter

status. It is low when a conversion is in progress. Data

valid on the rising edge of BUSY.

VSS (Pin 26): – 5V Negative Supply. Bypass to AGND

using 10

µF tantalum in parallel 0.1µF or 10µF ceramic.

OVDD (Pin 27): Positive Supply for Output Drivers. For

5V logic, short to Pin 28. For 3V logic, short to supply

of the logic being driven.

AVDD (Pin 28): 5V Positive Supply. Bypass to AGND

µF tantalum in parallel with 0.1µF or 10µF ceramic.

Load Circuits for Bus Relinquish Time

Load Circuits for Access Timing

100pF

DBN

LTC1409 • TC02

DBN

LTC1409 • TC01

(a) Hi-Z to VOH

and VOL to VOH

(b) Hi-Z to VOL

and VOH to VOL

(a) VOH to Hi-Z

(b) VOL to Hi-Z

FU CTIO AL BLOCK DIAGRA

12-BIT CAPACITIVE DAC

COMP

REF AMP

2.5V REF

REFCOMP

(4.06V)

CSAMPLE

•

D11

BUSY

CONTROL LOGIC

CONVST

SHDN

INTERNAL

CLOCK

NAP/SLP

ZEROING SWITCHES

OVDD

OGND

AVDD

+AIN

–AIN

VREF

AGND

DGND

LTC1409 • BD

–

SUCCESSIVE APPROXIMATION

OUTPUT LATCHES

TEST CIRCUITS

LTC1409CSW 데이터시트(PDF) 7 Page - Linear Technology

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