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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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LF48410 데이터시트(PDF) 5 Page - LOGIC Devices Incorporated |
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LF48410 데이터시트(HTML) 5 Page - LOGIC Devices Incorporated |
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5 / 15 page  DEVICES INCORPORATED Video Imaging Products 5 LF48410 1024 x 24-bit Video Histogrammer 08/08/2000–LDS.48410-L example, to set the number of delays to 10, START would have to be set LOW every 6 cycles. The maximum delay length is 1029 and the minimum delay length is 6. Data on DIN23-0 is latched on the rising edge of CLK and loaded into the memory array at the address defined by the counter. Data is output on DIO23-0 (if RD is LOW). If the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled. DELAY AND SUBTRACT MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 6. The internal counter is used to gener- ate address data for the memory array. When START goes LOW, the counter is reset to zero. Delay length (row length) is determined by reseting the counter every N–4 clock cycles, where N is the number of delays. The maximum delay length is 1029 and the minimum delay length is 6. Data on DIN23-0 is latched on the rising edge of CLK and loaded into the memory array at the address defined by the counter. Data is output on DIO23-0 (if RD is LOW). Before data read from the memory array is output to DIO23-0, input data is subtracted from it according to the following formula: OUTC = D(C–N+1) – D(C–3). OUTC is the data sent to the output port (DIO23-0) on clock cycle C. D(C–N+1) is the data latched into the device on clock cycle C–N+1, and D(C- 3) is the data latched into the device on clock cycle C–3. N is the number of delays. For example, to determine what will be output on DIO23-0 on clock cycle 12 when the device is set for 10 delays, set C=12 and N=10 to obtain: OUT12 = D3 – D9. If the counter reaches the value of 1023, the counter will hold this value and writing to the memory array will be disabled. ASYNCHRONOUS 16 MODE When the LF48410 is in this mode, the chip is configured as shown in Figure 7. This mode allows the device to function as an asynchronous single port RAM. Each 24-bit memory location is split into two parts, the lower 16 bits and the upper 8 bits. IOA9-0 addresses the 24-bit memory locations, and UWS addresses the lower 16 or upper 8 bits of those locations. If UWS is LOW, the lower 16 bits of the 24-bit memory location are addressed. If UWS is HIGH, the upper 8 bits are addressed. Address data on IOA9-0 and UWS is latched into the device on the falling edge of RD or WR. If RD latches the address data, a memory read is performed. Data at the specified address is output on DIO15-0 (if UWS was latched LOW) or DIO7-0 (if UWS was latched HIGH). If UWS was latched LOW/HIGH, DIO16-23/DIO8-23 will output zeros during a memory read. If WR latches the address data, a memory write is performed. After the falling edge of WR latches the address, data on DIO15-0 (if UWS was latched LOW) or DIO7-0 (if UWS was latched HIGH) is written to the RAM on the rising edge of WR. FIGURE 6. DELAY AND SUBTRACT MODE FIGURE 5. DELAY MEMORY MODE RAM ARRAY DATA IN DATA OUT ADDRESS CONTROL START DIO I/F DIO23-0 24 RD CLK COUNTER (TO ALL REGISTERS) DIN23-0 24 NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS. –DIN23-0 WR RAM ARRAY DATA IN DATA OUT ADDRESS CONTROL START "0" DIO I/F DIO23-0 24 RD CLK COUNTER (TO ALL REGISTERS) DIN23-0 24 NOTE: NUMBER IN REGISTER INDICATES NUMBER OF PIPELINE DELAYS. WR |
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