ICS8543BGI REVISION E NOVEMBER 15, 2012

5

©2012 Integrated Device Technology, Inc.

ICS8543I Data Sheet

LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

AC Electrical Characteristics

All parameters measured at 500MHz unless noted otherwise.

NOTE 1: Measured from the differential input crossing point to the differential output crossing point.

NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.

Measured at the differential output crosspoints.

NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using

the same type of inputs on each device, the outputs are measured at the differential crosspoints.

NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input High Current

PCLK

150

µA

nPCLK

5

µA

Input Low Current

PCLK

-5

µA

nPCLK

-150

µA

Peak-to-Peak Voltage; NOTE 1

0.3

1

V

Common Mode Input Voltage;

NOTE 1, 2

1.5

V

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Differential Output Voltage

200

280

360

mV

V

OD

0

40

mV

Offset Voltage

1.125

1.25

1.375

V

V

OS

5

25

mV

High Impedance Leakage

-10

+10

µA

Power Off Leakage

-20

±1

+20

µA

Differential Output Short Circuit

Current

-3.5

-5

mA

Output Short Circuit Current

-3.5

-5

mA

Output Voltage High

1.34

1.6

V

Output Voltage Low

0.9

1.06

V

Parameter

Symbol

Test Conditions

Minimum

Typical

Maximum

Units

Maximum Output Frequency

650

MHz

tjit

Buffer Additive Phase Jitter, RMS;

refer to Additive Phase Jitter Section

153.6MHz, Integration

Range: 12kHz – 20MHz

0.164

ps

Propagation Delay; NOTE 1

ƒ

 650MHz

1.5

2.6

ns

tsk(o)

Output Skew; NOTE 2, 4

40

ps

tsk(pp)

Part-to-Part Skew; NOTE 3, 4

600

ps

Output Rise/Fall Time

20% to 80% @ 50MHz

150

450

ps

odc

Output Duty Cycle

odc

45

50

55

%