ICS8543BGI REVISION E NOVEMBER 15, 2012

11

©2012 Integrated Device Technology, Inc.

ICS8543I Data Sheet

LOW SKEW, 1-to-4, DIFFERENTIAL-TO-LVDS FANOUT BUFFER

LVPECL Clock Input Interface

The PCLK /nPCLK accepts LVPECL, CML, SSTL and other

requirements. Figures 4A to 4F show interface examples for the S

PCLK/nPCLK input driven by the most common driver types. The

input interfaces suggested here are examples only. If the driver is

from another vendor, use their termination recommendation. Please

consult with the vendor of the driver component to confirm the driver

termination requirements.

Figure 4A. PCLK/nPCLK Input Driven by a

CML Driver

Figure 4C. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver

Figure 4E. PCLK/nPCLK Input Driven by an

SSTL Driver

Figure 4B. PCLK/nPCLK Input Driven by a

Built-In Pullup CML Driver

Figure 4D. PCLK/nPCLK Input Driven by a

3.3V LVPECL Driver with AC Couple

Figure 4F. PCLK/nPCLK Input Driven by a

3.3V LVDS Driver

PCLK

nPCLK

LVPECL

Input

CML

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

3.3V

R1

50

Ω

R2

50

Ω

R3

125

Ω

R4

125

Ω

R1

84

Ω

R2

84

Ω

3.3V

Zo = 50

Ω

Zo = 50

Ω

PCLK

nPCLK

3.3V

3.3V

LVPECL

LVPECL

Input

PCLK

nPCLK

LVPECL

Input

SSTL

2.5V

Zo = 60

Ω

Zo = 60

Ω

2.5V

3.3V

R1

120

R2

120

R3

120

R4

120

3.3V

R1

100

Ω

CML Built-In Pullup

PCLK

nPCLK

3.3V

LVPECL

Input

Zo = 50

Ω

Zo = 50

Ω

R3

84

R4

84

R1

125

R2

125

R5

100 - 200

R6

100 - 200

PCLK

nPCLK

3.3V LVPECL

3.3V

Zo = 50

Ω

Zo = 50

Ω

3.3V

3.3V

LVPECL

Input

C1

C2

3.3V

R1

100

Ω

LVDS

PCLK

nPCLK

3.3V

LVPECL

Input

Zo = 50

Ω

Zo = 50

Ω