S1004 datasheet(21/42 Pages) SII

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BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

Rev.2.1_00

S-1004 Series

Seiko Instruments Inc.

3. Delay circuit

The delay circuit has the function that adjusts the release delay time (tRESET) from when the SENSE pin voltage

(VSENSE) reaches release voltage (

+VDET) to when the output from OUT pin inverts.

tRESET is determined by the delay coefficient, the delay capacitor (CD), and the release delay time when the CD pin

is open (tRESET0), and calculated by the equation below.

tRESET [ms] = Delay coefficient

× CD [nF] + tRESET0 [ms]

Table 13

Operation

Temperature

Delay Coefficient

Min.

Typ.

Max.

Ta =

+85°C

1.78

2.29

3.13

Ta =

+25°C

2.30

2.66

3.07

Ta =

−40°C

2.68

3.09

3.57

Table 14

Operation

Temperature

Release Delay Time when CD Pin is Open (tRESET0)

Min.

Typ.

Max.

Ta =

+85°C

0.020 ms

0.049 ms

0.130 ms

Ta =

+25°C

0.021 ms

0.059 ms

0.164 ms

Ta =

−40°C

0.024 ms

0.074 ms

0.202 ms

Caution 1.

Mounted board layout should be made in such a way that no current flows into or flows from

the CD pin since the impedance of the CD pin is high, otherwise correct delay time cannot be

provided.

There is no limit for the capacitance of CD as long as the leakage current of the capacitor can

be ignored against the built-in constant current value (30 nA to 200 nA).

The detection delay time (tDET) cannot be adjusted by CD.

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