S1004 datasheet(32/42 Pages) SII

부품명	S1004

상세설명	BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)

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BUILT-IN DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING) VOLTAGE DETECTOR WITH SENSE PIN

S-1004 Series

Rev.2.1_00

Seiko Instruments Inc.

17. Release delay time (tRESET) vs. Power supply voltage (VDD)

S-1004Cx10

Ta =

+25°C,

CD = 4.7 nF

8.0

6.0

10.0

2.0

4.0

VDD [V]

0.0

s

tRESET

VIH*1

SENSE pin voltage

Output voltage

VIL*2

VDD

VSS

VDD

 90%

*1.

VIH = 10 V

*2.

VIL = 0.95 V

Figure 36 Test Condition of Release Delay Time

VDD

VSS

OUT

100 k

SENSE

P.G.

Oscilloscope

VDD

VSS

OUT

SENSE

P.G.

Oscilloscope

Figure 37 Test Circuit of Release Delay Time

Figure 38 Test Circuit of Release Delay Time

(Nch open-drain output product)

(CMOS output product)

Caution

The above connection diagram and constant will not guarantee successful operation.

Perform thorough evaluation using the actual application to set the constant.

S1004 데이터시트(PDF) 32 Page - Seiko Instruments Inc

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