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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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DB929B 데이터시트(PDF) 33 Page - CML Microcircuits |
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DB929B 데이터시트(HTML) 33 Page - CML Microcircuits |
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33 / 51 page  4-Level FSK Modem Data Pump Page 33 of 50 MX929B PRELIMINARY INFORMATION ©2001 MX-COM, INC. www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054 Doc. # 20480171.003 4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies. 5. Application 5.1 Transmit Frame Example The operations needed to transmit a single Frame consisting of Symbol and Frame Sync sequences, and one each Header, Intermediate and Last blocks are provided below: 1. Ensure that the Control Register has been loaded with a suitable CKDIV value, that the IRQEN and RX / TX bits of the Mode Register are '1', the RXEYE, PSAVE, and SSIEN bits are '0', and the INVSYM bit is set appropriately. 2. Read the Status Register to ensure that the BFREE bit is '1', then write 6 Symbol Sync bytes (a preamble) to the Data Block Buffer and a T24S task to the Command Register. 3. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 4. Write the 6 byte Frame Sync to the Data Block Buffer and a T24S task to the Command Register. 5. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 6. Write 3 Station ID bytes to the Data Block Buffer and a TSID task to the Command Register. 7. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 8. Write 10 Header Block bytes to the Data Block Buffer and a THB task to the Command Register. 9. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 10. Write 12 Intermediate Block bytes to the Data Block Buffer and a TIB task to the Command Register. 11. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be '1' and the IBEMPTY bit should be '0'. 12. Write 8 Last Block bytes to the Data Block Buffer and a TLB task to the Command Register. 13. Wait for an interrupt from the modem, read the Status Register; the IRQ and BFREE bits should be ‘1’ and the IBEMPTY bit should be ‘0’. 14. Wait for another interrupt from the modem, read the Status Register; the IRQ, BFREE and IBEMPTY bits should be '1'. Notes: 1. The final symbol of the frame will start to appear approximately 2 symbol times after the Status Register IBEMPTY bit goes to '1'; a further 16 symbol times should be allowed for the symbol to pass completely through the RRC filter. 2. The SSYM bits of the Mode Register may be altered at any time to change the transmitted ‘S’ symbols. If a timing reference is required, then setting the Mode Register SSIEN bit to ‘1’ will cause a PC interrupt after every ‘S’ symbol transmitted, in which case the PC will have to distinguish between interrupts caused by the BFREE bit going to ‘1’, and those caused by the SRDY bit being set to ‘1’. 3. Figure 19 and Figure 20 illustrate the host PC routines needed to send a single Frame consisting of Symbol and Frame Sync patterns, a Station ID Block, a Header block, and any number of Intermediate blocks and one Last Block. It is assumed that the Tx Interrupt Service Routine Figure 20 is called every time the MX929B IRQ output line goes low. |
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