DM385 datasheet(151/281 Pages) TI

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DEVOSC_MXI/

DEV_CLKIN

CLKOUT_MUX

CLKOUT0

1000

ARM Cortex-A8 Functional Clock / 16

CLKOUT1

1011-1111

RESERVED

1010

RCOSC32K Output

0111

AUX Clock

0110

DEV Clock

0101

PLL_L3L4 Output

0100

PLL_MEDIACTL Output / 2

0011

PLL_HDVPSS Output / 2

0010

PCIE SERDES Observation Clock

0001

SERDES Observation Clock

0000

PRCM SYSCLK Output

1001

PLL_AUDIO

CLKIN32

PLL_VIDEO0

PLL_HDVICP

PLL_HDVPSS

DM385, DM388

www.ti.com

SPRS821D – MARCH 2013 – REVISED DECEMBER 2013

Figure 7-12. CLKOUTx Source Selection Logic

For detailed information on the CLKOUTx switching characteristics, see Table 7-17.

7.4.5

Input/Output Clocks Electrical Data/Timing

Note: If an external clock oscillator is used, a single clean power supply should be used to power both the

device and the external clock oscillator circuit.

Table 7-14. Timing Requirements for DEVOSC_MXI/DEV_CLKIN(1) (2) (3)(see Figure 7-13)

OPP100

NO.

UNIT

MIN

NOM

MAX

tc(DMXI)

Cycle time, DEVOSC_MXI/DEV_CLKIN

33.33

tw(DMXIH)

Pulse duration, DEVOSC_MXI/DEV_CLKIN high

0.45C

0.55C

tw(DMXIL)

Pulse duration, DEVOSC_MXI/DEV_CLKIN low

0.45C

0.55C

tt(DMXI)

Transition time, DEVOSC_MXI/DEV_CLKIN

tJ(DMXI)

Period jitter, DEVOSC_MXI/DEV_CLKIN

0.02C

Frequency Stability

±50

ppm

(1)

The DEVOSC_MXI/DEV_CLKIN frequency and PLL settings should be chosen such that the resulting SYSCLKs and Module Clocks are

within the specific ranges shown in the Section 7.4.7, SYSCLKs and Section 7.4.8, Module Clocks.

(2)

The reference points for the rise and fall transitions are measured at VIL MAX and VIH MIN.

(3)

C = DEV_CLKIN cycle time in ns. For example, when DEVOSC_MXI/DEV_CLKIN frequency is 20 MHz, use C = 50 ns.

Figure 7-13. DEV_MXI/DEV_CLKIN Timing

Power, Reset, Clocking, and Interrupts

151

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