PIC18F010 datasheet(71/176 Pages) MICROCHIP

71 / 176 page

 2001 Microchip Technology Inc.

Preliminary

DS41142A-page 69

PIC18F010/020

FIGURE 9-4:

BLOCK DIAGRAM OF

RB4 PIN

FIGURE 9-5:

BLOCK DIAGRAM OF

RB5 PIN

Data Latch

From other

WPUBx(2)

VDD

I/O

Data Bus

WR LATB

WR TRISB

TRIS Latch

RD TRISB

RD PORTB

RB pins

Weak

Pull-up

RD PORTB

Latch

TTL

Input

Buffer

pin(1)

Note 1: I/O pins have diode protection to VDD and VSS.

CLKOUT

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the WPUB bit(s) and RBPU bit.

RD LATB

PORTB

Set RBIF

IOCB Register

WR IOCB

Data Latch

WPUBx(2)

VDD

I/O

Data Bus

WR LATB

WR TRISB

TRIS Latch

RD TRISB

RD PORTB

Weak

Pull-up

Latch

TTL

Input

Buffer

pin(1)

Note 1: I/O pins have diode protection to VDD and VSS.

Buffer

CLKIN

2: To enable weak pull-ups, set the appropriate TRIS bit(s)

and clear the WPUB bit(s) and RBPU bit.

RD LATB

PORTB

From other

RB pins

RD PORTB

IOCB Register

WR IOCB

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