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LP3961 데이터시트(PDF) 19 Page - Texas Instruments |
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LP3961 데이터시트(HTML) 19 Page - Texas Instruments |
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19 / 31 page ![]() Ground IN OUT SD ERROR Input Capacitor Output Capacitor Pullup Resistor Pullup Resistor LP3961, LP3964 www.ti.com SNVS056J – MAY 2000 – REVISED JUNE 2015 9 Power Supply Recommendations The LP396x devices are designed to operate from an input voltage supply range between 2.5 V and 7 V. The input voltage range provides adequate headroom in order for the device to have a regulated output. This input supply must be well regulated. An input capacitor of at least 68 μF is required. 10 Layout 10.1 Layout Guidelines Good PC layout practices must be used or instability can be induced because of ground loops and voltage drops. The input and output capacitors must be directly connected to the IN, OUT, and GND pins of the LP396x using traces which do not have other currents flowing in them (Kelvin connect). The best way to do this is to lay out CIN and COUT near the device with short traces to the IN, OUT, and GND pins. The regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a single-point ground. It should be noted that stability problems have been seen in applications where vias to an internal ground plane were used at the ground points of the LP396x IC and the input and output capacitors. This was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. Using a single- point ground technique for the regulator and its capacitors fixed the problem. Because high current flows through the traces going into the IN pin and coming from the OUT pin, Kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. 10.2 Layout Example Figure 26. LP3961 TO-263 Package Typical Layout Copyright © 2000–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: LP3961 LP3964 |
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