PIC17C752-08SLASHCL datasheet(43/328 Pages) MICROCHIP

43 / 328 page

DS30289A-page 43

PIC17C7XX

7.1.2

EXTERNAL MEMORY INTERFACE

When either microprocessor or extended microcontrol-

ler mode is selected, PORTC, PORTD and PORTE are

conﬁgured as the system bus. PORTC and PORTD are

the multiplexed address/data bus and PORTE<2:0> is

for the control signals. External components are

needed to demultiplex the address and data. This can

be done as shown in Figure 7-4. The waveforms of

address and data are shown in Figure 7-3. For com-

plete timings, please refer to the electrical speciﬁcation

section.

FIGURE 7-3:

EXTERNAL PROGRAM

MEMORY ACCESS

WAVEFORMS

The system bus requires that there is no bus conﬂict

(minimal leakage), so the output value (address) will be

capacitively held at the desired value.

As the speed of the processor increases, external

EPROM memory with faster access time must be used.

Table 7-2 lists external memory speed requirements for

a given PIC17C7XX device frequency.

<15:0>

ALE

'1'

Read cycle

Write cycle

Address out Data in

Address out

Data out

In extended microcontroller mode, when the device is

executing out of internal memory, the control signals

will continue to be active. That is, they indicate the

action that is occurring in the internal memory. The

external memory access is ignored.

This following selection is for use with Microchip

EPROMs. For interfacing to other manufacturers mem-

ory, please refer to the electrical speciﬁcations of the

desired PIC17C7XX device, as well as the desired

memory device to ensure compatibility.

TABLE 7-2:

EPROM MEMORY ACCESS

TIME ORDERING SUFFIX

The electrical speciﬁcations now include timing speciﬁ-

cations for the memory interface with PIC17LCXXX

devices. These speciﬁcations reﬂect the capability of

the device by characterization. Please validate your

design with these timings.

PIC17C7XX

Oscillator

Frequency

Instruction

Cycle

Time (TCY)

EPROM Sufﬁx

8 MHz

500 ns

-25

16 MHz

250 ns

-15

20 MHz

200 ns

-10

25 MHz

160 ns

-70

33 MHz

121 ns

(1)

Note 1: The access times for this requires the use of

fast SRAMs.

FIGURE 7-4:

TYPICAL EXTERNAL PROGRAM MEMORY CONNECTION DIAGRAM

AD7-AD0

PIC17CXXX

AD15-AD8

ALE

I/O(1)

AD15-AD0

Memory(3)

(MSB)

Ax-A0

D7-D0

A15-A0

Memory(3)

(LSB)

Ax-A0

D7-D0

138(1)

(2)

Note 1:

Use of I/O pins is only required for paged memory.

This signal is unused for ROM and EPROM devices.

16-bit wide devices are now common and could be used instead of 8-bit wide devices.

373(3)

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