16F628 datasheet(48/168 Pages) MICROCHIP

48 / 168 page

PIC16F627A/628A/648A

DS40044A-page 46

Preliminary

 2002 Microchip Technology Inc.

6.3

Timer0 Prescaler

An 8-bit counter is available as a prescaler for the

Timer0 module, or as a postscaler for the Watchdog

Timer. A prescaler assignment for the Timer0 module

means that there is no postscaler for the Watchdog

Timer, and vice-versa.

The PSA and PS2:PS0 bits (OPTION<3:0>) determine

the prescaler assignment and prescale ratio.

When assigned to the Timer0 module, all instructions

writing

the

TMR0

(e.g.,

CLRF 1,

MOVWF 1, BSF 1, x....etc.) will clear the pres-

caler. When assigned to WDT, a

CLRWDT instruction

will clear the prescaler along with the Watchdog Timer.

The prescaler is not readable or writable.

FIGURE 6-1:

BLOCK DIAGRAM OF THE TIMER0/WDT

T0CKI

T0SE

OSC/4

SYNC

CYCLES

TMR0 REG

8-TO-1MUX

WATCHDOG

TIMER

PSA

WDT

TIME OUT

PS0 - PS2

PSA

WDT ENABLE BIT

DATA BUS

SET FLAG BIT T0IF

ON OVERFLOW

PSA

Note:

T0SE, T0CS, PSA, PS0-PS2 are bits in the Option Register.

T0CS

WDT POSTSCALER/

TMR0 PRESCALER

TMR1 Clock Source

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