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MT4LC4M4E8DJS 데이터시트(PDF) 21 Page - Micron Technology |
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MT4LC4M4E8DJS 데이터시트(HTML) 21 Page - Micron Technology |
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21 / 23 page ![]() 4 Meg x 4 EDO DRAM Micron Technology, Inc., reserves the right to change products or specifications without notice. D47.pm5 – Rev. 3/97 ©1997, Micron Technology, Inc. 21 4 MEG x 4 EDO DRAM TECHNOLOGY, INC. SELF REFRESH CYCLE (Addresses and OE# = DON’T CARE) V V IH IL RAS# tRASS OPEN V V IH IL V V OH OL DQ tRPC tCHD tRPS tRPC tRP tCP CAS# , ,,, ,, WE# V V IH IL tWRH tWRP ,, ,, ,,, ,,,, ,,,, ,, tWRH tWRP ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) ( ) NOTE 1 tCSR ,, ,,,, ,,, ,,, ,,, , ,, ,, DON'T CARE UNDEFINED tCP NOTE 2 ( ) ( ) ( ) ( ) NOTE: 1. Once tRASS (MIN) is met and RAS# remains LOW, the DRAM will enter Self Refresh mode. 2. Once tRPS is satisfied, a complete burst of all rows should be executed. -5 -6 SYMBOL MIN MAX MIN MAX UNITS tRPC 5 5 ns tRPS 90 105 ns tWRH 8 10 ns tWRP 8 10 ns TIMING PARAMETERS -5 -6 SYMBOL MIN MAX MIN MAX UNITS tCHD 15 15 ns tCP 8 10 ns tCSR 5 5 ns tRASS 100 100 µs tRP 30 40 ns |
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