MT9V024 datasheet(40/62 Pages) ONSEMI

40 / 62 page

MT9V024_DSRev. G Pub. 4/15 EN

©Semiconductor Components Industries, LLC, 2015.

MT9V024: 1/3-Inch Wide-VGA Digital Image Sensor

Feature Description

Pixel Clock Speed

The pixel clock speed is same as the master clock (SYSCLK) at 26.66 MHz by default.

However, when column binning 2 or 4 (R0x0D or R0x0E, bit 2 or 3) is enabled, the pixel

clock speed is reduced by half and one-fourth of the master clock speed respectively. See

“Read Mode Options” on page 36 and “Column Binning” on page 37 for additional infor-

mation.

Hard Reset of Logic

The RC circuit for the MT9V024 uses a 10kresistor and a 0.1µF capacitor. The rise time

for the RC circuit is 1µs maximum.

Soft Reset of Logic

Soft reset of logic is controlled by:

•R0x0C Reset

Bit 0 is used to reset the digital logic of the sensor while preserving the existing two-wire

serial interface configuration. Furthermore, by asserting the soft reset, the sensor aborts

the current frame it is processing and starts a new frame. Bit 1 is a shadowed reset

control register bit to explicitly reset the automatic gain and exposure control feature.

These two bits are self-resetting bits and also return to “0” during two-wire serial inter-

face reads.

STANDBY Control

The sensor goes into standby mode by setting STANDBY to HIGH. Once the sensor

detects that STANDBY is asserted, it completes the current frame before disabling the

digital logic, internal clocks, and analog power enable signal. To release the sensor out

from the standby mode, reset STANDBY back to LOW. The LVDS must be powered to

ensure that the device is in standby mode. See "Appendix A: Power-On Reset and

Standby Timing" on page 54 for more information on standby.

Monitor Mode Control

Monitor mode is controlled by:

• R0xD9 Monitor Mode Enable

• R0xC0 Monitor Mode Image Capture Control

The sensor goes into monitor mode when R0xD9[0] is set to HIGH. In this mode, the

sensor first captures a programmable number of frames (R0xC0), then goes into a sleep

period for five minutes. The cycle of sleeping for five minutes and waking up to capture a

number of frames continues until R0xD9[0] is cleared to return to normal operation.

In some applications when monitor mode is enabled, the purpose of capturing frames is

to calibrate the gain and exposure of the scene using automatic gain and exposure

control feature. This feature typically takes less than 10 frames to settle. In case a larger

number of frames is needed, the value of R0xC0 may be increased to capture more

frames.

During the sleep period, none of the analog circuitry and a very small fraction of digital

logic (including a five-minute timer) is powered. The master clock (SYSCLK) is therefore

always required.

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