UCD7138DRST datasheet(13/36 Pages) TI

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VCC

OUT

DTC

VCC(ON)

VCC(OFF)

UCD7138

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SLVSCS1B – MARCH 2015 – REVISED MAY 2015

Feature Description (continued)

8.3.2 Gate Turnon and Turnoff

Gate turnon is controlled by both the gate driver input, IN, and body-diode conduction. System robustness is

enhanced through internal logic that guarantees that OUT is only allowed high if IN is also high. At the IN rising

edge, the UCD7138 gate-driver analyzes the DTC signal and determines the required course of action. The OUT

pin is sent high immediately if the DTC comparator output is low at the rising edge of the IN signal. If the DTC pin

is high at the rising edge of the IN signal, OUT is held low until DTC goes low. To allow the gate turnon edge to

optimize freely, setting the dead time between the primary side falling edge and the IN rising edge smaller than

expected in the UCD3138A digital controller is recommended.

The gate turnoff edge is determined by the IN signal only. The gate is turned off immediately at the IN falling

edge.

Table 1. Truth Table for CTRL Pin Function

CTRL PIN CONFIGURATION

FUNCTION

0 V or ground

Turn-on optimization disabled

3.3 V or floating

Turn-on optimization enabled

8.3.3 VCC and Undervoltage Lockout

The UCD7138 device has an internal undervoltage-lockout (UVLO) protection feature based on the VCC-pin

voltage. Whenever the driver is in the UVLO condition (such as when the VCC voltage is less than VCC(ON) during

power up or when the VCC voltage is less than VCC(OFF) during power down), the device holds all outputs low,

regardless of the status of the inputs. The UVLO voltage is typically 3.8 V with a 240-mV hysteresis. This

hysteresis helps prevent chatter when low VCC supply voltages have noise from the power supply and also when

droops occur in the VCC bias voltage.

For example, at power up, the UCD7138 driver output remains low until the VCC voltage reaches the UVLO

threshold. The magnitude of the OUT signal rises with VCC until steady-state VCC is reached. The output remains

low until the UVLO threshold is reached. The DTC signal begins to rise when VCC begins to rise. The internal

diode conduction detection comparator remains inactive until VCC passes VCC(ON) threshold.

Figure 25. Device Power Up and Power Down

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