GP2010

9

Notes on Pin Descriptions

see Fig. 7.

2). The Digital Interface supply is independent from all the other supply pins, allowing supply separation to reduce the likelihood

of undesirable digital signals interfering with the IF strip. (Note the maximum allowable Power Supply Differential in the

Electrical Characteristics - page 4).

3). The 35.42MHz Bandpass filter should have a bandwidth of approx 2.0MHz. Ideally, this should be a DW9255 SAW filter.

LH

Power Down

Normal Operation

Powered Down

TEST

Normal Operation

Test

CONTROL SIGNALS

OPERATING NOTES

A typical application circuit is shown in figure 4 with the

GP2010 front-end interfaced to the GP2021 12 channel

correlator integrated circuit. The RF input has an unmatched

input impedance (see page 4). The RF input matching com-

ponents Cs and Cp should be mounted as close to the RF

input as possible: also the Vee(RF) tracks must be kept as

short as possible. A SAW may be used as a 175.42MHz filter,

but this can be replaced by a simpler coupled-tuned LC filter

if there is no critical out-of band jamming immunity require-

ment. The DC bias to mixer 1 is provided via inductors L1 and

L2, which may form part of the 175.42MHz filter. The output

of mixer 2 requires an external dc bias, achieved with inductors

L3 and L4, which also serve to tune out the input capacitance

of the DW9255 SAW filter. The output of the SAW is tuned with

inductor L5. The AGC capacitor (Cagc) determines the AGC

time-constant. The PLL loop filter components are selected to

give a PLL loop bandwidth of approx. 10kHz. The IF Output

is normally used for test-purposes only, but is available to the

user if required. Typically a low noise preamplifier (gain

>+15dB) is used, and may be located with a remote antenna.

Fig. 3 GP2010 test circuit

Stage

2

Stage

3

AGC Control

M1

M2

M3

M4

RF

INPUT

Cs

Stage 1

Output

175 MHz

Stage 2

Input

175 MHz

Stage 2

Output

35 MHz

Stage 3

Input

35 MHz

C1

C2

R1

IF

Output

CLK

SIGN

MAG

Cagc

OPClk

LD

REF 2

TEST

PDn

1

12

22

PLL

LOOP

FILTER

PRESET PREF

21

13

11

44

43

41

40

37

36

34

33

29

2

Cp

3

14

15

19

PLL

SYNTHESISER

24

18

Power

Down

17

Power

Detect

98

AGC Control

ADC

Stage

3

M4

M3

Stage

2

M2

M1

Stage

1

M1 - 4 = Matching

Networks, incorporating

Balun transformers

C1

= 470nF

C2

= 10nF

R1

= 270

Ω

Cagc = 100nF

Cs

= 5pF

Cp

= 1.5pF

QUALITY AND RELIABILITY

At Mitel Semiconductor, quality and reliability are built

into products by rigorous control of all processing operations,

and by minimising random, uncontrolled effects in all manu-

facturing operations. Process management involves full docu-

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A common information management system is used to

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and Bipolar processes. All products benefit from the use of an

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Further information is contained in the Quality Bro-

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