GP2015

5

MHz

MHz

V

MHz/V

V/rad

V pk-pk

k

Ω

ms

dB

V

V

µA

µA

V

V

ns

V

V

mV p-p

%

V

V

V

µA

(Note 4)

(Note 7)

Pin 27

(Note 11)

From Power up (Note 7)

(Note 7)

Pins 11, 19, 20

Pins 15, 14

CL = 15pF, RL = 15k

Ω (Note 7)

Pins 16 & 17

(Note 5)

CL = 15pF (GND) (Note 7)

CL = 5pF (Diff) (Note 7)

(Note 7)

Pins 21 and 9

Pin 8

1386

3.5

240

1.2

0.5

10

0.5

0.5

1.35

10

Characteristic

Value

Typ.

Max.

Min.

3.3

150

5.3

0.6

5

6

150

20

220

43

0.2

Conditions

Units

1414

3

50

0.1

2

0

-300

1.1

-10

VCO Maximum Lock Frequency

VCO Minimum Lock Frequency

VCO regulator output voltage

VCO Gain

Phase Detector Gain

10MHz Reference Input

10MHz Reference Input Impedance

PLL Lockup Time

PLL Loop Gain

DIGITAL INTERFACES

Sample Clock, Power Down,

Test Inputs.

Sign/Mag Outputs

Sample Clock to Sign/Mag Delay

40MHz Clock Output

Output (differential)

Duty Cycle

LD (PLL Lock)/PReset Outputs

Power-on Reset comparator input

Power Reset Reference Level

Power Reset Reference Input Current

Notes On Electrical Characteristics:- All RF measurements are made with appropriate matching to the input or output

impedances, such as balun transformers, and levels refer to matched 50ohm ports (see figure 3 for test circuit)

1.

RF input impedance (series) without input matching components connected - expressed as Real impedance with reactive

inductor value. Measured at 1575.42MHz.

2.

Input matched to 50ohm, output loaded wlth 600ohm differential

3.

Maximum Stage 3 input signal amplitude for correct AGC operation = 20mV rms.

4.

VCO regulator voltage measured with respect to Vcc (OSC) - pin 5.

5.

6.

Minimum gain requirement expressions:

-7dBm < -174dBm/Hz + 19dB + G1 + G2 + G3 - 21dB + 63dB

where -7dBm = typical IF Output level with AGC active (equivalent to 100mV rms)

-174dBm/Hz = background noise level at RF input

19dB = sum of LNA gain and noise figure

-21dB = total loss in 175MHz and 35MHz filters

63dB = summation of noise over a 2MHz bandwidth

Rearranging the above expression gives G1 + G2 + G3 > 106dB.

7.

This parameter is not production tested.

8.

This impedance is toleranced at +/-30% and is not production tested.

9.

Roll off occurs in on-chip capacitive coupling IF Output to input of ADC circuit. Not measurable at IF Output.

10. CW input on pins 47 & 48 of 35.42MHz at 7mV rms.

11. This input impedance applies to the typical input level. The impedance is level dependent and is not tested or guaranteed.