PIC16F84A datasheet(13/68 Pages) MICROCHIP

13 / 68 page

PIC16F84A

Preliminary

DS35007A-page 13

3.0

I/O PORTS

Some pins for these I/O ports are multiplexed with an

alternate function for the peripheral features on the

device. In general, when a peripheral is enabled, that

pin may not be used as a general purpose I/O pin.

Additional information on I/O ports may be found in the

PICmicro™

Mid-Range

Reference

Manual,

(DS33023).

3.1

PORTA and TRISA Registers

PORTA is a 5-bit wide bi-directional port. The corre-

sponding data direction register is TRISA. Setting a

TRISA bit (=1) will make the corresponding PORTA pin

an input, i.e., put the corresponding output driver in a

hi-impedance mode. Clearing a TRISA bit (=0) will

make the corresponding PORTA pin an output, i.e., put

the contents of the output latch on the selected pin.

Reading the PORTA register reads the status of the

pins whereas writing to it will write to the port latch. All

write operations are read-modify-write operations.

Therefore a write to a port implies that the port pins are

read, this value is modiﬁed, and then written to the port

data latch.

Pin RA4 is multiplexed with the Timer0 module clock

input to become the RA4/T0CKI pin. The RA4/T0CKI

pin is a Schmitt Trigger input and an open drain output.

All other RA port pins have TTL input levels and full

CMOS output drivers.

EXAMPLE 3-1:

INITIALIZING PORTA

BCF

STATUS, RP0

;

CLRF

PORTA

; Initialize PORTA by

; clearing output

; data latches

BSF

STATUS, RP0

; Select Bank 1

MOVLW

0x0F

; Value used to

; initialize data

; direction

MOVWF

TRISA

; Set RA<3:0> as inputs

; RA4 as output

; TRISA<7:5> are always

; read as '0'.

FIGURE 3-1:

BLOCK DIAGRAM OF PINS

RA3:RA0

Note:

On a Power-on Reset, these pins are con-

ﬁgured as inputs and read as '0'.

Note: I/O pins have protection diodes to VDD and VSS.

Data

bus

Port

TRIS

Data Latch

TRIS Latch

RD TRIS

RD PORT

TTL

input

buffer

VSS

VDD

I/O pin

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