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SD6830P 데이터시트(PDF) 14 Page - AUK corp |
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SD6830P 데이터시트(HTML) 14 Page - AUK corp |
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14 / 34 page ![]() KSI-W002-000 14 Figure 6-6. Rest structure and Release Timing for STOP Mode to Normal Mode 6.14 OSC Divide Option The OSC divide option provides a maximum 1MHz system clock (F SYS). FOSC which is generated in oscillation circuit is divided eight or non-divide to produce F SYS. This dividing ratio will be selected by mask option. F OSC : Oscillator clock, F SYS : System clock (FOSC or FOSC/8) Figure 6-7 OSC Divide Option 7. Electrical Specifications 7.1 Absolute maximum ratings Symbols Parameters Conditions Ratings Units V DD Supply Voltage -0.3 ~ 6.0 V V I Input Voltage -0.3 ~ V DD + 0.3 V V O Output Voltage Ta=25℃ -0.3 ~ V DD + 0.3 V T OPR Operating temperature - -20 ~ 85 ℃ T STG Storage Temperature - -40 ~ 125 ℃ SD6830 Internal /STOP Key input ( PORT D or PORT E ) OSCOUT STOP instruction 27mS(Min.) Normal mode Stop mode Stop mode VDD PORT D PORT E 4 4 STOP RESET STOP instruction internal /POR WDT overflow DMC6830 OSC DIVIDE-8 MASK OPTION OSC OUT FOSC F SYS OSC IN SD6830 |
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