ATmega16 datasheet(77/315 Pages) ATMEL

77 / 315 page

ATmega16(L)

2466E–AVR–10/02

Figure 37 shows the setting of OCF0 and the clearing of TCNT0 in CTC mode.

Figure 37. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with

Prescaler (f

clk_I/O/8)

8-bit Timer/Counter

Timer/Counter Control

• Bit 7 – FOC0: Force Output Compare

The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However,

for ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is

written when operating in PWM mode. When writing a logical one to the FOC0 bit, an

immediate compare match is forced on the Waveform Generation unit. The OC0 output

is changed according to its COM01:0 bits setting. Note that the FOC0 bit is implemented

as a strobe. Therefore it is the value present in the COM01:0 bits that determines the

effect of the forced compare.

A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode

using OCR0 as TOP.

The FOC0 bit is always read as zero.

• Bit 6, 3 – WGM01:0: Waveform Generation Mode

These bits control the counting sequence of the counter, the source for the maximum

(TOP) counter value, and what type of Waveform Generation to be used. Modes of

operation supported by the Timer/Counter unit are: Normal mode, Clear Timer on Com-

pare Match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes. See

Table 38 and “Modes of Operation” on page 71.

OCFn

OCRn

TCNTn

(CTC)

TOP

TOP - 1

TOP

BOTTOM

BOTTOM + 1

clk

I/O

clk

(clk

I/O/8)

Bit

FOC0

WGM00

COM01

COM00

WGM01

CS02

CS01

CS00

TCCR0

Read/Write

R/W

Initial Value

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