ATmega16 datasheet(71/315 Pages) ATMEL

71 / 315 page

ATmega16(L)

2466E–AVR–10/02

Figure 30. Compare Match Output Unit, Schematic

The general I/O port function is overridden by the Output Compare (OC0) from the

Waveform Generator if either of the COM01:0 bits are set. However, the OC0 pin direc-

tion (input or output) is still controlled by the Data Direction Register (DDR) for the port

pin. The Data Direction Register bit for the OC0 pin (DDR_OC0) must be set as output

before the OC0 value is visible on the pin. The port override function is independent of

the Waveform Generation mode.

The design of the output compare pin logic allows initialization of the OC0 state before

the output is enabled. Note that some COM01:0 bit settings are reserved for certain

modes of operation. See “8-bit Timer/Counter Register Description” on page 77.

Compare Output Mode and

Waveform Generation

The Waveform Generator uses the COM01:0 bits differently in normal, CTC, and PWM

modes. For all modes, setting the COM01:0 = 0 tells the waveform generator that no

action on the OC0 Register is to be performed on the next compare match. For compare

output actions in the non-PWM modes refer to Table 39 on page 78. For fast PWM

mode, refer to Table 40 on page 78, and for phase correct PWM refer to Table 41 on

page 79.

A change of the COM01:0 bits state will have effect at the first compare match after the

bits are written. For non-PWM modes, the action can be forced to have immediate effect

by using the FOC0 strobe bits.

Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare

pins, is defined by the combination of the Waveform Generation mode (WGM01:0) and

Compare Output mode (COM01:0) bits. The Compare Output mode bits do not affect

the counting sequence, while the Waveform Generation mode bits do. The COM01:0

bits control whether the PWM output generated should be inverted or not (inverted or

non-inverted PWM). For non-PWM modes the COM01:0 bits control whether the output

should be set, cleared, or toggled at a compare match (See “Compare Match Output

Unit” on page 70.).

For detailed timing information refer to Figure 34, Figure 35, Figure 36 and Figure 37 in

“Timer/Counter Timing Diagrams” on page 75.

PORT

DDR

OCn

Waveform

Generator

COMn1

COMn0

FOCn

clk

I/O

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