ATmega16 datasheet(135/315 Pages) ATMEL

135 / 315 page

135

ATmega16(L)

2466E–AVR–10/02

hardware when executing the corresponding interrupt handling vector. Alternatively, the

SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing

the SPI Data Register (SPDR).

• Bit 6 – WCOL: Write COLlision flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register

with WCOL set, and then accessing the SPI Data Register.

• Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega16 and will always read as zero.

• Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when

the SPI is in Master mode (see Table 58). This means that the minimum SCK period will

be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-

teed to work at fosc/4 or lower.

The SPI interface on the ATmega16 is also used for program memory and EEPROM

downloading or uploading. See page 268 for SPI Serial Programming and Verification.

SPI Data Register – SPDR

The SPI Data Register is a read/write register used for data transfer between the regis-

ter file and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register Receive buffer to be read.

Data Modes

There are four combinations of SCK phase and polarity with respect to serial data,

which are determined by control bits CPHA and CPOL. The SPI data transfer formats

are shown in Figure 67 and Figure 68. Data bits are shifted out and latched in on oppo-

site edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is

clearly seen by summarizing Table 56 and Table 57, as done below:

Bit

765

432

MSB

LSB

SPDR

Read/Write

R/W

Initial Value

Undefined

Table 59. CPOL and CPHA Functionality

Leading Edge

Trailing Edge

SPI Mode

CPOL = 0, CPHA = 0

Sample (Rising)

Setup (Falling)

CPOL = 0, CPHA = 1

Setup (Rising)

Sample (Falling)

CPOL = 1, CPHA = 0

Sample (Falling)

Setup (Rising)

CPOL = 1, CPHA = 1

Setup (Falling)

Sample (Rising)

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