ATmega16 datasheet(217/315 Pages) ATMEL

217 / 315 page

217

ATmega16(L)

2466E–AVR–10/02

The IEEE std. 1149.1 also specifies an optional TAP signal; TRST – Test ReSeT –

which is not provided.

When the JTAGEN Fuse is unprogrammed, these four TAP pins are normal port pins,

and the TAP controller is in reset. When programmed, the input TAP signals are inter-

nally pulled high and the JTAG is enabled for Boundary-scan and programming. The

device is shipped with this fuse programmed.

For the On-chip Debug system, in addition to the JTAG interface pins, the RESET pin is

monitored by the debugger to be able to detect external reset sources. The debuggerbta

can also pull the RESET pin low to reset the whole system, assuming only open collec-

tors on the reset line are used in the application.

Figure 112. Block Diagram

TAP

CONTROLLER

TDI

TDO

TCK

TMS

FLASH

MEMORY

AVR CPU

DIGITAL

PERIPHERAL

UNITS

JTAG / AVR CORE

COMMUNICATION

INTERFACE

BREAKPOINT

UNIT

FLOW CONTROL

UNIT

OCD STATUS

AND CONTROL

INTERNAL

SCAN

CHAIN

INSTRUCTION

BYPASS

JTAG PROGRAMMING

INTERFACE

Instruction

Address

Data

BREAKPOINT

SCAN CHAIN

ADDRESS

DECODER

I/O PORT 0

I/O PORT n

BOUNDARY SCAN CHAIN

DEVICE BOUNDARY

ATMEGA16 데이터시트(PDF) 217 Page - ATMEL Corporation

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