LIS2DS12 datasheet(47/68 Pages) STMICROELECTRONICS

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LIS2DS12

8.14

FIFO_CTRL (25h)

FIFO control register 5 (r/w).

Table 51. FIFO control register

When the FIFO has been enabled, data acquired has been stored at the accelerometer

ODR and the trigger signal of FIFO writing is the accelerometer internal data-ready.

FIFO data can be stored in default configuration where inertial data as been stored as X, Y,

Z data or in module configuration:

Default configuration: 256-level inertial data (14-bit stored data for X, Y, Z)

User-selectable: 768 module data (14-bit each module)

FMODE2

FMODE1

FMODE0

INT2_STEP_

COUNT_OV

MODULE_

TO_FIFO

0(1)

1. This bit must be set to '0' for correct device operation.

0(1)

IF_CS_PU_

DIS

Table 52. FIFO control register description

FMODE [2:0]

FIFO mode selection bits. Default: 000. For further details refer to Table 53.

INT2_STEP_

COUNT_OV

Step counter overflow interrupt enable on INT2 pad. Default value: 0

(0: disabled; 1: enabled)

MODULE_TO_

FIFO

When set to '1'-logic, module routine result is send to FIFO instead of X,Y,Z

acceleration data

IF_CS_PU_DIS

When '1'-logic disconnects pull-up in if_cs pad. Default: 0

Table 53. FIFO mode selection

FMODE2 FMODE1

FMODE0

Mode

Bypass mode: FIFO turned off

FIFO mode: Stops collecting data when FIFO is full.

Reserved

Continuous-to-FIFO: Stream mode until trigger is deasserted,

then FIFO mode

Bypass-to-Continuous: Bypass mode until trigger is deasserted,

then FIFO mode

Reserved

Continuous mode: data If the FIFO is full, the new sample over-

writes the older sample.

Reserved

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