TMG39921 datasheet(67/95 Pages) AMSCO

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[v1-04] 2014-Oct-24

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TMG3992 − Register Description

Configuration Register A7 (CONFIG_A7),

IRBeam Mode

While IRBeam is enabled, this register defines the number of

nibbles in Symbol bit-pattern RAM (0x00 to 0x7F) that will be

processed to modulate a bit-pattern on the LDR during a single

symbol transmission. Each bit stored in a RAM location

corresponds to a single Bit-time. Since ILEN is measured in

nibbles (half-bytes) the smallest burst out of the LDR pin is four

bit-times. The largest burst time is 1024 bit-times. The following

equation describes the number of nibbles processed as a

function of register setting value:

ISLEN = Number of Nibbles - 1

Figure 71:

Configuration Register A7

Configuration Register A8 (CONFIG_A8),

IRBeam Mode

While IRBeam is enabled, this register provides the status of the

IRBeam state machine. This register is read only.

Figure 72:

Configuration Register A8

765

432

ISLEN

Field

Bits

Description

ISLEN

7:0

IRBeam Symbol bit-pattern Length in nibbles. Any write to this register

initiates an IRBeam event. ISLEN is the number of nibbles to burst out of

LDR/LED.

765

432

Reserved

PBINT2

PBUSY

Field

Bits

Description

Reserved

7:2

Reserved.

PBINT2

Pattern Burst Interrupt Two. A high logic level indicates that an IRBeam event

has run to completion. This bit is reset using the PBCLEAR register is written.

The same bit can also be accessed in STATUS register to permit the CPU

detection of interrupt cause with a single I²C read transaction.

PBUSY

Pattern Burst Busy. Indicates a Pattern burst (IRBeam transmission) is in

progress.

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