ADP5054ACPZ-R7 datasheet(19/31 Pages) AD

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Data Sheet

ADP5054

Rev. B | Page 19 of 31

Note that careful design and proper component selection are

required to ensure that the buck regulator recovers from hiccup

mode under heavy loads. The hiccup detection can be disabled

by the factory fuse for each buck regulator. When hiccup

detection is disabled, the frequency foldback feature is still

used for overcurrent protection.

LATCH-OFF PROTECTION

The buck regulators in the ADP5054 have an optional latch-off

mode to protect the device from serious problems such as

short-circuit conditions. Latch-off mode can be enabled via

the factory fuse.

Short-Circuit Latch-Off Mode

Short-circuit latch-off mode is enabled by the factory fuse. When

short-circuit latch-off mode is enabled and the protection circuit

detects an overcurrent status after a soft start, the buck regulator

enters hiccup mode and attempts to start up again. If seven

continuous retry attempts are made and the regulator remains

in the fault condition, the regulator is shut down. This shutdown

(latch-off) condition is cleared only by reenabling the channel

or by resetting the channel power supply.

The operation of short-circuit latch-off protection is shown in

Figure 38.

OUTPUT

VOLTAGE

TIME

LATCH-OFF

LATCH OFF

THIS

REGULATOR

SHORT CIRCUIT DETECTED

BY COUNTER OVERFLOW

PWRGD

7 ×

tSS

SCP LATCH-OFF

FUNCTION ENABLED AFTER

7 RETRY ATTEMPTS

ATTEMPT TO

RESTART

Figure 38. Short-Circuit Latch-Off Detection

Note that short-circuit latch-off mode does not work if hiccup

detection is disabled.

UNDERVOLTAGE LOCKOUT (UVLO)

Undervoltage lockout circuitry monitors the input voltage level

of each buck regulator in the ADP5054. If any input voltage

(PVINx pin) falls below 3.79 V (typical), the corresponding

channel is turned off. After the input voltage rises above 4.22 V

(typical), the soft start period is initiated, and the corresponding

channel is enabled when the ENx pin is high.

Note that a UVLO condition on Channel 1 (PVIN1 pin) has a

higher priority than a UVLO condition on other channels,

which means that the PVIN1 supply must be available before

other channels can be operated.

POWER-GOOD FUNCTION

The ADP5054 includes an open-drain power-good output

(PWRGD pin) that becomes active high when the Channel 1

buck regulators are operating normally.

A high status on the PWRGD pin indicates that the regulated

output voltage of the buck regulator is above 90.5% (typical) of

its nominal output. When the regulated output voltage of the

buck regulator falls below 87.2% (typical) of its nominal output

for a delay time greater than approximately 50 µs, the status of

the PWRGD pin is set low.

The PWRGD pin can be programmed by the factory fuse to

indicate the outputs of other specific channels.

THERMAL SHUTDOWN

If the ADP5054 junction temperature exceeds 150°C, the

thermal shutdown (TSD) circuit turns off the IC except for the

internal linear regulator. Extreme junction temperatures can be

the result of high current operation, poor circuit board design, or

high ambient temperature. A 15°C hysteresis is included so that

the ADP5054 does not return to operation after thermal

shutdown until the on-chip temperature falls below 135°C.

When the device exits thermal shutdown, a soft start is initiated

for each enabled channel.

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