Rev 1.0, May 18, 2006

Page 2 of 15

SL23EP08

Pin Configuration

CLKA1

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

FBK

CLKA4

CLKA3

VDD

GND

CLKB4

CLKB3

S1

CLKIN

CLKA2

VDD

GND

CLKB1

CLKB2

S2

Pin Description

16-Pin SOIC and TSSOP

Pin

Number

Pin Name

Pin Type

Pin Description

1

CLKIN

Input

Reference Frequency Clock Input. 5V tolerant input. Weak pull-down (2

50kΩ).

2

CLKA1

Output

Buffered Clock Output, Bank A. Weak pull-

down (250kΩ).

3

CLKA2

Output

Buffered Clock Output, Bank A. Weak pull-

down (250kΩ).

4

VDD

Power

3.3V or 2.5V Power Supply.

5

GND

Power

Power Ground.

6

CLKB1

Output

Buffered Clock Output, Bank B. Weak pull-

down (250kΩ).

7

CLKB2

Output

Buffered Clock Output, Bank B. Weak pull-

down (250kΩ).

8

S2

Input

Select Input, select pin S2. Weak pull-

up (250kΩ).

9

S1

Input

Select Input, select pin S1. Weak pull-

up (250kΩ).

10

CLKB3

Output

Buffered Clock Output, Bank B. Weak pull-

down (250kΩ).

11

CLKB4

Output

Buffered Clock Output, Bank B. Weak pull-

down (250kΩ).

12

GND

Power

Power Ground.

13

VDD

Power

3.3V or 2.5V Power Supply.

14

CLKA3

Output

Buffered Clock Output, Bank A. Weak pull-

down (250kΩ).

15

CLKA4

Output

Buffered Clock Output, Bank A. Weak pull-

down (250kΩ).

16

FBK

Output

PLL Feedback input.