Rev 1.0, May 18, 2006

Page 4 of 15

SL23EP08

Device

Feedback From

Bank-A Frequency

Bank-B Frequency

SL23EP08-1

Bank-A or Bank-B

Reference

Reference

SL23EP08-1H

Bank-A or Bank-B

Reference

Reference

SL23EP08-2

Bank-A

Reference

Reference/2

SL23EP08-2

Bank-B

2x Reference

Reference

SL23EP08-3

Bank-A

2X Reference

Reference

[2]

SL23EP08-3

Bank-B

4X Reference

2X Reference

SL23EP08-4

Bank-A or Bank-B

2X Reference

2X Reference

SL23EP08-5H

Bank-A or Bank-B

Reference /2

Reference /2

Table 3. Available SL23EP08 Configurations

Notes:

1. Outputs are inverted on SL23EP08-2 and SL23EP08-3 in PLL bypass mode when S2=1 and S1=0.

2. Output phase is either 0° or 180° with respect to CLKIN input. If phase integrity is required, use the SL23EP08-2.

0

5

10

15

20

25

30

-30

-25

-20

-5

-10

-15

1500

1000

500

-500

-1500

-1000

0

Output Load Difference: FBK Load – CLKA or CLKB Load (pF)

Figure 1. CLKIN Input to CLKA and CLKB Delay