DLPR910

DLPS065A – SEPTEMBER 2015 – REVISED OCTOBER 2015

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Feature Description (continued)

7.3.1.2 Configuration Clock Input

The configuration CLK is connected to the DLPC910 in master mode, where the DLPC910 provides the clock

pulses to read the configuration from the DLPR910.

7.3.1.3 Output Enable and Reset

When the OE/(RESET) input is held low, the address counter is reset and the Data and CLKOUT outputs are

placed in high-impedance state. OE/(RESET) must be pulled High using an external 4.7-k

7.3.1.4 Chip Enable

The (CE) input is asserted by the DLPC910 to enable the Data and CLKOUT outputs. When (CE) is held high,

the DLPR910 address counter is reset, and the Data and CLKOUT outputs are placed in high-impedance states.

7.3.1.5 Configuration Pulse

The DLPR910 is configured in serial mode when the Configuration Pulse (CF) is held high and (CE) and OE are

enabled. New data is available a short time after each rising clock edge.

7.3.1.6 Revision Selection

REV_SEL_0, REV_SEL_1, and (EN_EXT_SEL) signals are used for selecting which revision to be the default.

Setting all three signals to GND will default to revision 0 for simple DLPR910 setup.

7.4 Device Functional Modes

To successfully program the DLPC910 upon power-up, the DLPR910 must be configured and connected to the

DLPC910 as shown in Figure 2.

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