USB3320 datasheet(11/70 Pages) MICROCHIP

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 2014-2015 Microchip Technology Inc.

DS00001792B-page 11

USB3320

4.2

Clock Specifications

Note 4-3

The Suspend Recovery Time is measured from the start of the REFCLK to when the USB3320 de-

asserts DIR.

4.3

ULPI Interface Timing

Note 4-4

REFCLK

does not need to be aligned in any way to the ULPI signals.

TABLE 4-2:

ULPI CLOCK SPECIFICATIONS

Parameter

Symbol

Condition

MIN

TYP

MAX

Units

Suspend Recovery Time

Note 4-3

TSTART

26MHz REFCLK

1.03

2.28

12MHz REFCLK

2.24

3.49

52MHz REFCLK

0.52

1.77

24MHz REFCLK

1.12

2.37

19.2MHz REFCLK

1.40

2.65

27MHz REFCLK

1.00

2.25

38.4MHz REFCLK

0.70

1.95

13MHz REFCLK

2.07

3.32

PHY Preparation Time

TPREP

60MHz REFCLK

ULPI Input Clock Mode

0.40.450.5

CLKOUT

Duty Cycle

DCCLKOUT

ULPI Input Clock Mode

REFCLK

Duty Cycle

DCREFCLK

REFCLK

Frequency Accuracy

FREFCLK

-500

+500

PPM

Note:

The USB3320 uses the AutoResume feature, Section 6.2.4.4, to allow a host start-up time of less than

1ms.

TABLE 4-3:

ULPI INTERFACE TIMING

Parameter

Symbol

Condition

MIN

TYP

MAX

60MHz ULPI Output Clock

Note 4-4

Setup time (STP, data in)

TSC, TSD Model-specific REFCLK

5.0

Hold time (STP, data in)

THC, THD Model-specific REFCLK

0.0

Output delay (control out, 8-bit data out)

TDC, TDD Model-specific REFCLK

1.0

3.5

60MHz ULPI Input Clock

Setup time (STP, data in)

TSC, TSD 60MHz REFCLK

1.5

Hold time (STP, data in)

THC, THD 60MHz REFCLK

-0.5

Output delay (control out, 8-bit data out)

TDC, TDD 60Mhz REFCLK

1.5

6.0

Note:

VDD18 = 1.6 to 2.0V; VSS = 0V; TA = -40°C to +85°C.

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