SPEAR320S datasheet(104/113 Pages) STMICROELECTRONICS

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Timing requirements

SPEAr320S

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Doc ID 022508 Rev 2

The above min. and max. values allow a deviation of

±1 baud cycle in a single bit time. The

accumulated deviation of a UART character frame must not exceed 3/(16*fbaudrate).

For information related to baud rate generation refer to:

●

Section 2.12: Asynchronous serial ports (UART)

●

RM0321, Reference manual, SPEAr320S address map and registers

Figure 38.

RS485_OE transmit and receive waveform

Table 79.

UART transmit timing characteristics

Symbol

Parameters

Min

Max

Unit

fbaudrate

UART1 .. UART6 baud rate

6(1)

Maximum baudrate = 6 Mbps provided that UARTCLK is within a frequency range greater than 96 MHz

and less than 5/3 PCLK.

Mbps

UART0 baud rate

tBIT

UART duration of transmit data bit (B0..B7),

Parity bit (Pbit), Start bit, Stop bits(2)

tUARTCLK = 1/fUARTCLK with fUARTCLK in MHz

1/fbaudrate -

tUARTCLK -1

1/fbaudrate +

tUARTCLK +1

Table 80.

UART receive timing characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

tBIT

Pulse duration of receive data (B0

..B7), Parity bit (Pbit), Start bit,

Stop bits(1)

The time margin is with respect to a single bit accumulation and not with respect to the whole UART frame.

The start bit is sampled after the 8th baud cycle after a low is detected at input, Subsequently, each bit is

sampled at consecutive 16 baud cycles.

Baudrate = 6

Mbps

1/fbaudrate -

(tUARTCLK/2)

1/fbaudrate +

(tUARTCLK/2)

1/fbaudrate -1/

(16*fbaudrate)

1/fbaudrate +

(16*fbaudrate)

UARTTXD

Start

bit

Stop

bit

Pbit

UARTRXD

Start

bit

Stop

bit

Pbit

tD1

tD2

RS485_OE

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