L9959 datasheet(38/49 Pages) STMICROELECTRONICS

38 / 49 page

SPI functional description

L9959

38/49

DocID027540 Rev 2

Note:

Only the bits ‘CONFIG’ and ‘DIACLR’ in this register can be written, all other bits are ‘read-

only’

Table 34. Current Level (CONFIG_REG)

CL1

CL2

Current Level

Typical Current

No Change

5.0 A

3 (default value)

6.6 A

8.6 A

Table 35. Status and configuration register (STATCON_REG)

Bit

Name

CONFIG2

CONFIG1

CONFIG0

DIACLR2

DIACLR1

STATUS2

STATUS1

STATUS0

Bit

Name

Content

CONFIG2

VDD Test Threshold:

0: VDD Threshold Test is on 1: VDD Threshold test is off

CONFIG1

VDD Test Threshold:

1: Lower VDD Test Threshold is lifted 0:Upper VDD Test Threshold is lowered

CONFIG0

VDD Over-Voltage Latch: 0: Latch is disabled 1: Latch is enabled

DIACLR2

Reset DIA_REG2:

0: Reset errors in DIA_REG2 1: No action (Reading this bit always returns „1.)

DIACLR1

Transfer Errors:

0: All latched errors of DIA_REG1 are transferred to DIA_REG2. DIA21,DIA20, DIA11,

DIA10are set to “1111”.

During VS-Undervoltage DIACLR1 is disabled 1: No action (Reading this bit always

returns „1.)

STATUS2

Logic Level at Pin /ABE

STATUS1

VDD Under-Voltage:

0: Under-Voltage

1: No Under-Voltage

STATUS0

VDD Over-Voltage:

0: Over-Voltage

1: No Over-Voltage

This information is not reset during VS-Undervoltage. It will be reset by CONFIG0, SPI

reset or internal VDD reset

Reset(5.4.1)

POR

SPIR

ENDISR

RDR

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