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M24C64-DRMF8TP 데이터시트(PDF) 30 Page - STMicroelectronics

부품명 M24C64-DRMF8TP
상세설명  64-Kbit serial IC bus EEPROM - 105C operation
PDF  41 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

M24C64-DRMF8TP 데이터시트(HTML) 30 Page - STMicroelectronics

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DC and AC parameters
M24C64-DRE
30/40
DocID027358 Rev 1
Table 11. 400 kHz AC characteristics
Symbol
Alt.
Parameter(1)
1. Test conditions (in addition to those in Table 7 and Table 8).
Min.
Max.
Unit
fC
fSCL
Clock frequency
-
400
kHz
tCHCL
tHIGH
Clock pulse width high
600
-
ns
tCLCH
tLOW
Clock pulse width low
1300
-
ns
tQL1QL2 (2)
2. Characterized value, not tested in production.
tF
SDA (out) fall time (3)
3. With CL = 10 pF.
20
120
ns
tXH1XH2
tR
Input signal rise time
(4)
4. There is no min. or max. values for the input signal rise and fall times. It is however
recommended by the I²C specification that the input signal rise and fall times be more than 20
ns and less than 300 ns when fC < 400 kHz.
(4)
ns
tXL1XL2
tF
Input signal fall time
(4)
(4)
ns
tDXCH
tSU:DAT Data in set up time
100
-
ns
tCLDX
tHD:DAT Data in hold time
0
-
ns
tCLQX (5)
5. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and
the falling or rising edge of SDA.
tDH
Data out hold time
100
-
ns
tCLQV (6)
6. tCLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either
0.3VCC or 0.7VCC, assuming that Rbus × Cbus time constant is within the values specified in
Figure 10.
tAA
Clock low to next data valid (access time)
-
900
ns
tCHDL
tSU:STA Start condition setup time
600
-
ns
tDLCL
tHD:STA Start condition hold time
600
-
ns
tCHDH
tSU:STO Stop condition set up time
600
-
ns
tDHDL
tBUF
Time between Stop condition and next Start
condition
1300
-
ns
tWLDL(2)(7)
7. WC=0 set up time condition to enable the execution of a WRITE command.
tSU:WC WC set up time (before the Start condition)
0
-
µs
tDHWH(2)(8)
8. WC=0 hold time condition to enable the execution of a WRITE command.
tHD:WC WC hold time (after the Stop condition)
1
-
µs
tW
tWR
Write time
-
4
ms
tNS(2)
-
Pulse width ignored (input filter on SCL and
SDA) - single glitch
-80
ns



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