M95M01-DWMN3TP datasheet(15/40 Pages) STMICROELECTRONICS

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M95M01-A125 M95M01-A145

Instructions

Each command is composed of bytes (MSBit transmitted first), initiated with the instruction

byte, as summarized in Table 6.

If an invalid instruction is sent (one not contained in Table 6), the device automatically enters

a Wait state until deselected.

For read and write commands to memory array and Identification Page, the address is

defined by three bytes as explained in Table 7.

Table 6. Instruction set

Instruction

Description

Instruction

format

WREN

Write Enable

0000 0110

WRDI

Write Disable

0000 0100

RDSR

Read Status Register

0000 0101

WRSR

Write Status Register

0000 0001

READ

Read from Memory Array

0000 0011

WRITE

Write to Memory Array

0000 0010

RDID

Read Identification Page

1000 0011

WRID

Write Identification Page

1000 0010

RDLS

Reads the Identification Page lock status.

1000 0011

LID

Locks the Identification page in read-only mode.

1000 0010

Table 7. Significant bits within the address bytes(1) (2)

Instruction

Upper address byte

b23 b22 ... b17 b16

Middle address byte

b15 b14 ... b10 b9 b8

Lower address byte

b7 b6 ... b2 b1 b0

READ or WRITE

x x ... x A16

A15 A14 ... A10 A9 A8

A7 A6 ... A1 A0

RDID or WRID

0 0 ... 0 0

0 ... 0

0 0

A7 A6 ... A1 A0

RDLS or LID

0 0 ... 0 0

0 0 0 0 . 0 1 0 0

0 0 ... 0 0

1. A: Significant address bit.

2. x: bit is Don’t Care.

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